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monolithic cmos receiver 3.3v supply voltage low-jitter, on-chip clock recovery 256xfs output clock provided supports: aes/ebu, iec 958, s/pdif, & eiaj cp-340/1201 professional and consumer formats extensive error reporting repeat last sample on error option description the STA120 is a monolithic cmos device that receives and decodes audio data according to the aes/ebu, iec 958, s/pdif, & eiaj cp- 340/1201 interface standards. the STA120 recovers the clock and synchroniza- tion signals and de-multiplexes the audio and digital data. differential or single ended inputs can be decoded. the STA120 de-multiplexes the channel, user and validity data directly to serial output pins with dedicated output pins for the most important channel status bits. april 2002 ? audio serial port registers de mux clock & data recovery c0/e0 m2 m0 agnd filt sdata sck fsync c u vref erf cbl rxp 9 25 15 26 12 11 23 18 6 1 14 28 d97au613a m1 24 va+ mck 8 7 dgnd vd+ 19 21 20 22 rs422 receiver rxn 10 mux 13 cs12/fck 16 sel mux ca/e1 5 cb/e2 4 cc/f0 3 cd/f1 2 ce/f2 27 m3 17 block diagram ordering number: STA120d (so28) STA120 digital audio interface receiver 1/14
absolute maximum ratings symbol parameter value unit v d+ ,v a+ power supply voltage 4 v v in input voltage -0.3 to v d+ +0.3 v t amb ambient operating temperature (power applied) -30 to +85 c t stg storage temperature -40 to 150 c c0/e0 vd+ dgnd rxp rxn sck fsync cs12/fck u 1 3 2 4 5 6 7 8 9 cbl sel m3 mck m2 filt agnd va+ m0 23 22 21 20 19 17 18 16 15 d97au609a 10 11 12 13 14 28 27 26 25 24 c cd/f1 cc/f0 cb/e2 ca/e1 m1 erf sdata ce/f2 verf pin connection (top view) recommended operating conditions (gnd = 0v; all voltages with respect to ground) symbol parameter test condition min. typ. max. unit v d+ ,v a+ power supply voltage 3.0 3.3 3.6 v t amb ambient operating temperature -20 25 85 c STA120 2/14
pins description n. name function power supply 7v d+ positive digital power. positive supply for the digital section. nominally 3.3v. 8 dgnd digital ground. ground for the digital section. 21 agnd analog ground. ground for the analog section. agnd should be connected to same ground as dgnd. 22 v a+ positive analog power. positive supply for the analog section. nominally 3.3v. audio output interface 11 fsync frame sync. delineates the serial data and may indicate the particular channel, left or right and may be an input or output. the format is based on m0, m1, m2 and m3 pins. 12 sck serial clock. serial clock for sdata pin which can be configured (via the m0, m1, m2 and m3 pins) as an input or output and can sample data on the rising or falling edge. as an output, sck will generate 32 clocks for every audio sample. as an input, 32 sck periods per audio sample must be provided in all normal modes. 17, 18 23, 24 m2, m3 m1, m0 serial port mode selects. selects the format of fsync and the sample edge of sck with respect to sdata. 26 sdata serial data. audio data serial output pin. control pins 1 c channel status output. received channel status bit serial output port. fsync may be used to latchthis bit externally. except in i 2 s modes when this pin is updated at the active edge off fsync. 2 cd channel status output bits. these pin are dual function with the oco bits selected when sel is high. channel status information is displayed for the channel selected by cs12. c0, which is channel status bit 0, defines professional (c0 = 0) or consumer (c0 = 1) mode and further controls the definition of the ca-ce pins. these pins are updated with the rising edge of cbl. f1 frequency reporting bits. encoder sample frequency information that is enabled by bringing sel low. a proper clock on fck must be input for at least two thirds of a channel status block for these pins to be valid. they are updated three times per block, starting at the block boundary. 3 cc channel status output bits. these pin are dual function with the oco bits selected when sel is high. channel status information is displayed for the channel selected by cs12. c0, which is channel status bit 0, defines professional (c0 = 0) or consumer (c0 = 1) mode and further controls the definition of the ca-ce pins. these pins are updated with the rising edge of cbl. f0 frequency reporting bits. encoded sample frequency information that is enabled by bringing sel low. a proper clock on fck must be input for at least two thirds of a channel status block for these pins to be valid. they are updated three times per block, starting at the block boundary. 4 cb channel status output bits. these pin are dual function with the oco bits selected when sel is high. channel status information is displayed for the channel selected by cs12. c0, which is channel status bit 0, defines professional (c0 = 0) or consumer (c0 = 1) mode and further controls the definition of the ca-ce pins. these pins are updated with the rising edge of cbl. e2 error condition. encoded error information that is enabled by bringing sel low. the error codes are prioritized and latched so that the error code displayed is the highest level of error since the last clearing of the error pins. clearing is accomplished by bringing sel high for more than 8 mck cycles. 5 ca channel status output bits. these pin are dual function with the oco bits selected when sel is high. channel status information is displayed for the channel selected by cs12. c0, which is channel status bit 0, defines professional (c0 = 0) or consumer (c0 = 1) mode and further controls the definition of the ca-ce pins. these pins are updated with the rising edge of cbl. STA120 3/14
pins description (continued) n. name function 5 e2 error condition. encoded error information that is enabled by bringing sel low. the error codes are prioritized and latched so that the error code displayed is the highest level of error since the last clearing of the error pins. clearing is accomplished by bringing sel high for more than 8 mck cycles. 6 c0 channel status output bits. these pin are dual function with the oco bits selected when sel is high. channel status information is displayed for the channel selected by cs12. c0, which is channel status bit 0, defines professional (c0 = 0) or consumer (c0 = 1) mode and further controls the definition of the ca-ce pins. these pins are updated with the rising edge of cbl. e0 error condition. encoded error information that is enabled by bringing sel low. the error codes are prioritized and latched so that the error code displayed is the highest level of error since the last clearing of the error pins. clearing is accomplished by bringing sel high for more than 8 mck cycles. 13 cs12 channel select. this pin is also dual function and is selected by bringing sel high. cs12 selects sub-frame1 (when low) or sub-frame2 (when high) to be displayed by channel status pins c0 an ca through ce. fck frequency clock. frequency clock input that is enabled by bringing sel low. fck is compared to the received clock frequency with the value displayed on f2 through f0. nominal input value is 6.144mhz. 14 u user bit. received user bit serial output port, fsync may be used to latch this bit externally. except in i 2 s modes when this pin is updated at the active edge off fsync. 15 cbl channel status block start. the channel status block output is high for the first four bytes of channel status and low for the last 20 bytes. 16 sel select. control pin that selects either channel status information (sel = 1) or error and frequency information (sel = 0) to be displayed on six (c0, ca cb, cc, cd, ce) pins. 27 ce channel status output bits. these pin are dual function with the oco bits selected when sel is high. channel status information is displayed for the channel selected by cs12. c0, which is channel status bit 0, defines professional (c0 = 0) or consumer (c0 = 1) mode and further controls the definition of the ca-ce pins. these pins are updated with the rising edge of cbl. f2 frequency reporting bits. encoded sample frequency information that is enabled by bringing sel low. a proper clock on fck must be input for at least two thirds of a channel status block for these pins to be valid. they are updated three times per block, starting at the block boundary. 28 verf validity + error flag. a logical or'ing of the validity bit from the received data and the error flag. may be used by interpolation filters to interpolate through errors. receiver interface 9 rxp line receiver. (rs422 compatible) 10 rxn line receiver. (rs422 compatible) phase locked loop 19 mck master clock. low jitter clock output of 256 times the received sample frequency. 20 filt filter. an external 330 ohm resistor and 0.47 m f capacitor in parallel with a 15nf capacitor is required from filt pin to analog ground. 25 erf error flag, signals that an error has occurred while receiving the audio sample currently being read from the serial port. three errors cause erf to go high: a parity or biphase coding violation during the current sample, or an out of lock pll receiver. STA120 4/14
digital characteristics (t amb =25 c; v d+ ,v a+ = 3.3v 10%) symbol parameter test condition min. typ. max. unit v ih high-level input voltage 2.0 v v il low-level input voltage +0.8 v v oh high-level output voltage i o = 200 m av dd -1.0 v v ol low-level output voltage i o = 3.2ma 0.4 v i in input leakage current 1.0 10 m a f s input sample frequency (note 1) 25 55 khz mck master clock frequency (note 1) 6.4 256xf s 25 mhz t j mck clock jitter 300 ps rms mck duty cycle (high time/cycle time) 50 % i dd_st static i dd (mck = 0) 0.1 1 ma i dd_dyn dynamic idd 30 60 ma note 1 :f s is defined as the incoming audio sample frequency per channel. switching characteristics - serial ports (t amb =25 c; v d+ ,v a+ = 3.3v 10%) symbol parameter test condition min. typ. max. unit f sck sck frequency (note 2) owrx32 hz note 2 : the output word rate, owr, refers to the frequency at which an audio sample is output from the part. (a stereo pair is two audio samples). therefore, in master mode, there are always 32 sck periods in one audio sample. in slave mode 32 sck periods must be provided in most serial port formats. 10 audio data processor m controller or logic receiver circuit (see appendix a) rxn sck fsync 7 vd+ STA120 3.3v analog 22 va+ agnd 21 0.1 m f verf 19 sdata 26 11 c 1 cbl 15 d97au611 3.3v digital 0.1 m f 20 filt 15nf 0.47 m f 330 w 8 dgnd u 14 mck 28 12 9 rxp channel status and/or error/frequency reporting 13 cs12/fck 16 sel 25 erf 6 c/e-f bits figure 1. circuit diagram STA120 5/14
general description the STA120 is a monolithic cmos circuit that re- ceives and decodes audio and digital data ac- cording to the aes/ebu, iec 958, s/pdif, and eiaj cp-340/1201 interface standards. it contains a rs422 line receiver and phase- locked loops (pll) that recovers the clock and synchronization signals and de-multiplexes the audio and digital data. the STA120 de-multi- plexes the channel status, user and validity infor- mation directly to serial output pins with dedi- cated pins for the most important channel status bits. line receiver the line receiver can decode differential as well as single ended inputs. the receiver consits of a differential input schmitt trigger with 50mv of hys- teresis. the hysteresis prevents noisy signals from corrupting the phase detector. appendix a contains more information on how to configure the line receivers for differential and single ended signals. clocks and jitter attenuation the primary function of this chip is to recover audio data and low jitter clocks from a digital audio transmission line. the clocks that can be generated are mck (256xfs), sck (64xfs), and fsync (fs or 2xfs). mck is the output of the voltage controlled oscillator which is a component of the pll. the pll consists of phase and fre- quency detectors, a second-order loop filter, and a voltage controlled oscillator. all components of the pll are on chip with the exception of a resistor and capacitors used in the loop filter. this filter is connected between the filt pin and agnd. the closed-loop transfer function, which specifies the pll's jitter attenu- ation characteristics, is shown in figure 2. the loop will begin to attenuate jitter at approxi- mately 25khz with another pole at 80khz and will have 50db of attenuation by 1mhz. since most data jitter introduced by the transmission line is high in frequency, it will be strongly attenuated. multiple frequency detectors are used to minimize the time it takes the pll to lock to the incoming data stream and to prevent false lock conditions. when the pll is not locked to the incoming data stream, the frequency detectors pull the vco fre- quency within the lock range of the pll. when no digital audio data is present, the vco frequency is pulled to its minimum value. as a master, sck is always mck divided by four, producing a fre- quency of 64 x fs. in the STA120, fsync is al- ways generated from the incoming data stream. when fsync is generated from the data its edges are extracted at times when intersymbol interference is at a minimum. this provides a sample frequency clock that is as spectrally pure as the digital audio source clock for moderate length transmission lines. STA120 description the STA120 does not need a microprocessor to handle the non-audio data (although a micro may be used with the c and u serial ports). instead, dedicated pins are available for the most impor- tant channel status bits. the STA120 is a mono- lithic cmos circuits that receives and decodes digital audio data which was encoded according to the digital audio interface standards. it contains a clock and data recovery utilizing an on-chip phase-locked loop. the output data is output through a configurable serial port that supports 14 formats. the channel status and user data have their own serial pins and the validity flag is or'ed with the erf flag to provide a single pin, verf, indicating that the audio output may not be valid. this pin may be used by interpolation filters that provide error correction. audio serial port the audio serial port is used primarily to output audio data and consists of three pins: sck, fsync and sdata. these pins are configured via four control pins: m0, m1,m2,and m3.m3 se- lects between eight normal serial formats (m3 = 0), and six special formats (m3 = 1). normal modes (m3 = 0) when m3 is low, the normal serial port formats shown in figure 17 are selected using m2, m1 1 10 100 1000 (khz) 100 75 50 25 (db) d97au612 figure 2. jitter attenuator characteristics. STA120 6/14
and m0. these formats are also listed in table 1 wherein the first word part the format number (out-in) indicates whether fsync and sck are outputs from the STA120 or are inputs. the next word (l/r-wsync) indicates whether fsync indicates the particular channel or just delineates each word. if an error occurs (erf=1) while using one of these formats, the previous valid audio data for that channel will be output. if the STA120 is not locked, the last sample is re- peated at the output. in some modes fsync and sck are outputs and in others they are inputs. in table 3, lsbj is short for lsb justified where the lsb is justified to the end of the audio frame and the msb varies with word length. as outputs the STA120 generates 32 sck periods per audio sample (64 per stereo sample) and, as inputs, 32 sck periods must be provided per audio sample. when fsync and sck are inputs, one stereo sample is double buffered. for those modes which output 24 bits of audio data, the auxiliary bits will be included. if the auxiliary bits are not used for audio data, they must be masked off. table 1. normal audio port modes (m3 = 0) m2 m1 m0 format 0 0 0 0 - out, l/r, 16-24 bits 0 0 1 1 - in, l/r, 16-24 bits 0 1 0 2 - out, l/r, i 2 s compatible 0 1 1 3 - in, l/r, i 2 s compatible 1 0 0 4 - out, wsync, 16-24 bits 1 0 1 5 - out, l/r, 16 bits lsbj 1 1 0 6 - out, l/r, 18 bits lsbj 1 1 1 7 - out, l/r, msb last special modes (m3 = 1) when m3 is high, the special audio modes de- scribed in table 2 are selected via m2, m1, and m0. in formats 8, 9, and 10, sck, fsync, and sdata are the same as in formats 0, 1, and 2 re- spectively; however, the recovered data is output as is even if erf is high, indicating an error. (in modes 0-2 the previous valid sample is output). similarly, when out of lock, the STA120 will still output all the recovered data, which should be zeros if there is no input to the rxp, rxn pins. format 11 is similar to format 0 except that sck is an input and fsync is an output. in this mode fsync and sdata are synchro- nized to the incoming sck, this mode may be useful when writing data to storage. table 2. special audio port modes (m3 = 1) m2 m1 m0 format 0 0 0 8 - format 0 - no repeat on error 0 0 1 9 - format 1 - no repeat on error 0 1 0 10 - format 2 - no repeat on error 0 1 1 11 - format 0 - async. sck input 1 0 0 12 - received nrz data 1 0 1 13 - received bi-phase data 1 1 0 14 - reserved 1 1 1 15 - STA120 reset format 12 is similar to format 7 except that sdata is the entire data word received from the transmission line including the c, u, v, and p bits, with zeros in place of the preamble. in for- mat 13 sdata contains the entire biphase en- coded data from the transmission line including the preamble, and sck is twice the normal fre- quency. the normal two frame delay of data from input to output is reduced to only a few bit periods in for- mats 12 and 13. however, the c, u, v bits and error codes follow their normal pathways and therefore follow the output data by nearly two frames. figure 18.... illustrates formats 12 and 13. format 14 is reserved and not presently used, and format 15 causes the STA120 to go into a reset state. while in reset all outputs will be inactive except mck. the STA120 incorporates a power-on reset to avoid a reset at power-up. c, u, verf, erf, and cbl serial outputs the c and u bits and cbl are output one sck period prior to the active edge of fsync in all se- rial port formats except 2, 3 and 10 (i 2 s modes). the active edge of fsync may be used to latch c, u, and cbl externally.in formats 2, 3 and 10, the c and u bits and cbl are updated with the active edge of fsync. the validity + error flag (verf) and the error flag (erf) are always up- dated at the active edge of fsync. this timing is illustrated in figure 19. the c output contains the channel status bits with cbl rising indicating the start of a new chan- nel status block. cbl is high for the first four bytes of channel status (32 frames or 64 sam- ples) and low for the last 20 bytes of channel status (160 frames or 320 samples). the u output contains the user channel data. the v bit is or'ed with the erf flag and output on the verf pin. this indicates that the audio sample may be in error and can be used by in- terpolation filters to interpolate through the error. erf being high indicates a serious error occurred on the transmission line. there are three errors that cause erf to go high: a parity error or STA120 7/14
biphase coding violation during that sample, or an out of lock pll receiver. timing for the above pins is illustrated in figure 19. multifunction pins there are seven multifunction pins which contain either error and received frequency information, or channel status information, selectable by sel. fsync(out) msb lsb msb lsb msb left right sck(out) sdata(out) fsync(in) msb lsb msb lsb msb left right sck(in) sdata(out) fsync(out) msb lsb msb lsb msb left right sck(out) sdata(out) format 0: format 1: format 2: fsync(out) msb lsb msb lsb msb left right sck(out) sdata(out) fsync(out) lsb msb lsb sck(out) sdata(out) format 4: format 5: left right lsb msb 16 bits 16 bits fsync(out) lsb msb lsb sck(out) sdata(out) format 6: left right lsb msb 18 bits 18 bits fsync(out) msb lsb msb sck(out) sdata(out) format 7: left right msb lsb d97au610 m2 m1 m0 000 001 010 fsync(in) msb lsb msb lsb msb left right sck(in) sdata(out) format 3: 011 100 101 110 111 figure 3. audio serial port formats. STA120 8/14
error and frequency reporting when sel is low, error and received frequency information are selected. the error information is encoded on pins e2, e1, and e0, and is decoded as shown in table 5. when an error occurs, the corresponding error code is latched. clearing is then accomplished by bringing sel high for more than eight mck cycles. the errors have a priority associated with their error code, with validity having the lowest priority that oc- curred since the last clearing will be selected. table 5. error decoding e2 e1 e0 error 0 0 0 no error 0 0 1 validity bit high 0 1 0 confidence flag 0 1 1 slipped sample 1 0 0 crc error (pro only) 1 0 1 parity error 1 1 0 bi-phase coding error 1 1 1 no lock right 0 right 191 left 0 right 31 right 191 cbl c0 d98au988 left 0 left 1 left 32 sdata ca-ce fsync erf, verf c, u figure 19. cbl timing aux lsb left right msb v u c p aux lsb msb v u c p lsb left right msb lsb msb aux v u c p aux v u c p fsync(out) sck(out) sdata(out) fsync(out) sck(out) sdata(out) d98au987 figure 18. special audio port formats 12 and 13 STA120 9/14
the validity flag indicates that the validity bit for a previous sample was high since the last clearing of the error codes. the slipped sample error can only occur when fsync and sck of the audio serial port are inputs. in this case, if fsync is asynchronous to the received data rate, peri- odically a stereo sample will be dropped or re- read depending on whether the read rate is slower or faster than the received data rate \. when this occurs, the slipped sample error code will appear on the oeo pins. the crc error is updated at the beginning of a channel status block, and is only valid when the professional format of channel status data is re- ceived. this error is indicated when the STA120 calculated crc value does not match the crc byte of the channel status block or when a block boundary changes (as in removing samples while editing). the parity error occurs when the incoming sub- frame does not have even parity as specified by the standards. the biphase coding error indicates a biphase coding violation occurred. the no lock error indicates that the pll is not locked onto the incoming data stream. lock is achieved after re- ceiving three frame preambles then one block preamble, and is lost after not receiving four con- secutive frame preambles. the receive frequency information is encoded on pins f2, f1 and f0, and is decoded as shown in table 6. the on-chip frequency comparator com- pares the received clock frequency to an exter- nally supplied 6.144mhz clock which is input on the fck pin. the ofo pins. the clock on fck must be valid for two thirds of a block for the ofo pins to be accurate. table 6. sample frequency decoding f2 f1 f0 error 0 0 0 out of range 0 0 1 48khz 4% 0 1 0 44.1khz 4% 0 1 1 32khz 4% 1 0 0 48khz 400ppm 1 0 1 44.1khz 400ppm 1 1 0 44.056khz 400ppm 1 1 1 32khz 400ppm channel status reporting when sel is high, channel status is displayed on c0, and ca-ce for the channel selected by cs12. if cs12 is low, channel status for sub-frame1 is displayed, and if cs12 is high, channel status for subframe 2 is displayed. the contents of ca-ce depend upon the c0 professional/consumer bit. the information report is shown in table 7. table 7. channel status pins pin professional consumer c0 0 (low) 1 (high) ca c1 c1 cb em0 c2 cc em1 c3 cd c9 orig ce crce igcat professional channel status (c0 = 0) when c0 is low, the received channel status block is encoded according to the professional / broadcast format. the ca through ce pins are defined for some of the more important profes- sional bits. as listed in table 7, ca is the inverse of channel status bit1. therefore, if the incoming channel status bit1. therefore, if the incoming channel status bit 1 is 1, ca, defined as c1, will be 0. c1 indicates whether audio (c1 = 1) or non- audio (c1 = 0) data is being received. cb and cc, defined as em0 and em1 respectively, indicate emphasis and are encoded version of channel status bits 2, 3, and 4. the decoding is listed in table 8. cd, defined as c9, is the inverse of channel status bit 9, which gives some indication of channel status bit 9, which gives some indica- tion of channel mode. (bit 9 is also defined as bit 1 of byte 1). when ce, defined as crce, is low, the STA120 calculated crc value does not match the received crc value. this signal may be used to qualify ca through cd. if ca through ce are being displayed, ce going low can indi- cate not to update the display. table 8. emphasis encoding em1 em0 c2 c3 c4 emphasis 00111 ccitt j.17 emphasis 01110 50/15 m s emphasis 10100no emphasis 11000not indicated consumer channel status (c0 = 1) when c0 is high, the received channel status block is encoded according to the consumer for- mat. in this case ca through ce are defined dif- ferently as shown in table 7. ca is the inverse of channel status bit 1, c1, indi- cating audio (c1 = 1) or non-audio (c1 = 0). cb is defined as the inverse of channel status bit 2, c2, which indicates copy inhibit/copyright information. STA120 10/14
cc, defined as c3, is the emphasis bit of channel status, with c3 low indicating the data has had pre-emphasis added. the audio standards, in consumer mode, de- scribe bit 15, l, as the generation status which in- dicates whether the audio data is an original work or a copy (1st generation or higher). the defini- tion of the lbit is reversed for three category codes: two broadcast codes, and laser-optical (cd's). therefore, to interpret the l bit properly, the category code must be decoded. the STA120 does this decoding internally and pro- vides the orig signal that, when low, indicates that the audio data is original over all category codes. scms the consumer audio standards also mention a serial copy management system, scms, for deal- ing with copy protection of copyrighted works. scms is designed to allow unlimited duplication of the original work, but no duplication of any cop- ies of the original. this system utilizes the chan- nel status bit 2, copy, and channel status bit 15, l or generation status, along with the category codes. if the copy bit is 0, copyright protection is asserted over the material is an original or a du- plication. (as mentioned in the previous para- graph, the definition of the l bit can be reversed based on the category codes.) there are two category codes that get special attention: general and a/d converters without c or l bit information. for these two categories the scms standard re- quires that equipment interfacing to these catego- ries set the c bit to 0 (copyright protection as- serted) and the l bit to 1 (original). to support this feature, ce, in the consumer mode, is de- fined as igcat (ignorant category) which is low for the ogeneralo (0000000) and oa/d converter without copyright informationo (01100xx) catego- ries. appendix a: rs422 receiver information the rs422 receivers on the STA120 is designed to receive both the professional and consumer in- terfaces, and meet all specifications listed in the digital audio standards. figure 20 illustrates the internal schematic of the receiver portion of both chips. the receiver has a differential input. a schmitt trigger is incorporated to add hysteresis which prevents noisy signals from corrupting the phase detector. professional interface the digital audio specifications for professional use call for a balanced receiver, using xlr con- nectors, with 110 w 20% impedance. (the xlr connector on the receiver should have female pins with a male shell.) since the receiver has a very high impedance, a 110 w resistor should be placed across the receiver terminals to match the line impedance, as shown in figure 21, and, since the part has internal biasing, no external biasing network is needed. if some isolation is desired without the use of transformers, a 0.01 m f capaci- tor should be placed on the input of esch pin (rxp and rxn) as shown in figure 22. however, if transformers are not used, high frequency en- ergy could be coupled between transmitter and receiver causing degradation in analog perform- ance. although transformers are not required by aes they are strongly recommended. the ebu re- quires transformers. figure 21 and 22 show an optional dc blocking capacitor on the transmis- sion line. a 0.1 to 0.47 m f ceramic capacitor may be used to block any dc voltage that is acciden- tally connected to the digital audio receiver. the use of this capacitor is an issue of robustness s the digital audio transmission line does not have a dc voltage component. grounding the shield of the cables a tricky issue. in the configuration of systems, it is important to k-i x 1k 1k i x d98au983 rxp rxn figure 20. rs422 receiver internal circuit 110 w rxp rxn (*)see text 110 w twisted pair d98au984a xlr 1 figure 21. professional input circuit 110 w rxp rxn (*)see text 110 w twisted pair d98au985a xlr 1 0.01 m f 0.01 m f figure 22. transformerless professional cir- cuit STA120 11/14
avoid ground loops and dc current flowing down the shield of the cable that could results when boxes with different ground potentials are con- nected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and con- nect the shield through a capacitor to chassis ground at the receiver. however, in some cases it is advantageous to have the ground of two boxes help to the same potential, and the cable shield might be depended upon to make that electrical connection. generally, it may be a good idea to provide the option of grounding or capacitively coupling to ground with a oground-lifto circuit. consumer interface in the case of the consumer interface, the stand- ards call for an unbalanced circuit having a re- ceiver impedance of 75 w 5%. the connector for the consumer interface is an rca phono plug (fixed socket described in table iv of iec268-11). the receiver circuit for the consumer interface is shown in figure 23. ttl/cmos levels the circuit shown in figure 24 may be used when external rs422 receivers or ttl/cmos logic drive the STA120 receiver section. 75 w rxp rxn 75 w coax d02au1387 rca phono 100nf 100nf STA120 figure 23. consumer input circuit rxp rxn 100nf 100nf d98au986c STA120 figure 24. ttl/cmos interface STA120 12/14
so28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data STA120 13/14
information furnished is believed to be accurate and reliable. however, stmicroelectroni cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com STA120 14/14

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